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During the foreground calibration procedure, the ADC calculates a calibration factor which is
internally applied to the ADC until the next ADC power-off. The application must not use the
ADC during calibration and must wait until it is completed. Calibration should be performed
before starting A/D conversion. The calibration is initiated by setting bit CLB=1. CLB bit stays
at 1 during all the calibration sequence. It is then cleared by hardware as soon as the
calibration is completed.
When the ADC operating conditions change (such as supply power voltage VDDA, positive
reference voltage VREFP, temperature and so on), it is recommended to re-run a calibration
cycle. The internal analog calibration can be reset by setting the RSTCLB bit in ADC_CTL1 register.
Calibration software procedure:

Ensure that ADCON=1 => delay 14 CK_ADC to wait for ADC stability => Set RSTCLB (optional) => Set CLB=1 => Wait until CLB=0